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mh.h File Reference
#include "core.h"
#include "annotations.h"
#include "macros.h"
#include <cpuid.h>
#include "mm.h"

Go to the source code of this file.

Data Structures

struct  _IDT_PTR
struct  _IDT_ENTRY_64
struct  _RSDP_Descriptor
struct  _ACPI_SDT_HEADER
struct  _XSDT
struct  _GenericAddressStructure
struct  _FADT
struct  _MADT
struct  __attribute__
struct  _SMP_BOOTINFO
struct  _DEBUG_REGISTERS
struct  _PAGE_PARAMETERS
struct  _IPI_PARAMS

Macros

#define IDT_ENTRIES   256
#define IRQL_VECTOR_BASE   0x40
#define TPR_PASSIVE   0
#define TPR_APC   3
#define TPR_DPC   8
#define TPR_PROFILE   10
#define TPR_IPI   11
#define CALC_VECTOR(pri)
#define VECTOR_DPC   CALC_VECTOR(TPR_DPC)
#define VECTOR_APC   CALC_VECTOR(TPR_APC)
#define VECTOR_IPI   CALC_VECTOR(TPR_IPI)
#define LAPIC_TIMER_VECTOR   0xEF
#define AP_TRAMP_PHYS   0x7000ULL
#define AP_TRAMP_SIZE   0x1000UL
#define AP_TRAMP_APMAIN_OFFSET   0x1000ULL
#define AP_TRAMP_PML4_OFFSET   0x2000ULL
#define AP_TRAMP_CPUS_OFFSET   0x2500ULL
#define MAX_CPUS   32
#define LAPIC_ID   0x020
#define SMP_MAGIC   0x4D4154414E454C00
#define IST_SIZE   (16*1024)
#define IST_ALIGNMENT   16
#define CPUID_VENDOR_AMD   "AuthenticAMD"
#define CPUID_VENDOR_AMD_OLD   "AMDisbetter!"
#define CPUID_VENDOR_INTEL   "GenuineIntel"
#define CPUID_VENDOR_VIA   "VIA VIA VIA "
#define CPUID_VENDOR_TRANSMETA   "GenuineTMx86"
#define CPUID_VENDOR_TRANSMETA_OLD   "TransmetaCPU"
#define CPUID_VENDOR_CYRIX   "CyrixInstead"
#define CPUID_VENDOR_CENTAUR   "CentaurHauls"
#define CPUID_VENDOR_NEXGEN   "NexGenDriven"
#define CPUID_VENDOR_UMC   "UMC UMC UMC "
#define CPUID_VENDOR_SIS   "SiS SiS SiS "
#define CPUID_VENDOR_NSC   "Geode by NSC"
#define CPUID_VENDOR_RISE   "RiseRiseRise"
#define CPUID_VENDOR_VORTEX   "Vortex86 SoC"
#define CPUID_VENDOR_AO486   "MiSTer AO486"
#define CPUID_VENDOR_AO486_OLD   "GenuineAO486"
#define CPUID_VENDOR_ZHAOXIN   " Shanghai "
#define CPUID_VENDOR_HYGON   "HygonGenuine"
#define CPUID_VENDOR_ELBRUS   "E2K MACHINE "
#define CPUID_VENDOR_QEMU   "TCGTCGTCGTCG"
#define CPUID_VENDOR_KVM   " KVMKVMKVM "
#define CPUID_VENDOR_VMWARE   "VMwareVMware"
#define CPUID_VENDOR_VIRTUALBOX   "VBoxVBoxVBox"
#define CPUID_VENDOR_XEN   "XenVMMXenVMM"
#define CPUID_VENDOR_HYPERV   "Microsoft Hv"
#define CPUID_VENDOR_PARALLELS   " prl hyperv "
#define CPUID_VENDOR_PARALLELS_ALT   " lrpepyh vr "
#define CPUID_VENDOR_BHYVE   "bhyve bhyve "
#define CPUID_VENDOR_QNX   " QNXQVMBSQG "

Typedefs

typedef enum _CPU_EXCEPTIONS CPU_EXCEPTIONS
typedef enum _INTERRUPT_LIST INTERRUPT_LIST
typedef enum _CPU_ACTION CPU_ACTION
typedef struct _IDT_PTR IDT_PTR
typedef struct _IDT_ENTRY_64 IDT_ENTRY64
typedef struct _SMP_BOOTINFO SMP_BOOTINFO
typedef void(* DebugCallback) (void *)
typedef struct _DEBUG_REGISTERS DEBUG_REGISTERS
typedef struct _PAGE_PARAMETERS PAGE_PARAMETERS
typedef struct _IPI_PARAMS IPI_PARAMS

Enumerations

enum  _CPU_EXCEPTIONS {
  EXCEPTION_DIVIDE_BY_ZERO , EXCEPTION_SINGLE_STEP , EXCEPTION_NON_MASKABLE_INTERRUPT , EXCEPTION_BREAKPOINT ,
  EXCEPTION_OVERFLOW , EXCEPTION_BOUNDS_CHECK , EXCEPTION_INVALID_OPCODE , EXCEPTION_NO_COPROCESSOR ,
  EXCEPTION_DOUBLE_FAULT , EXCEPTION_COPROCESSOR_SEGMENT_OVERRUN , EXCEPTION_INVALID_TSS , EXCEPTION_SEGMENT_SELECTOR_NOTPRESENT ,
  EXCEPTION_STACK_SEGMENT_OVERRUN , EXCEPTION_GENERAL_PROTECTION_FAULT , EXCEPTION_PAGE_FAULT , EXCEPTION_RESERVED ,
  EXCEPTION_FLOATING_POINT_ERROR , EXCEPTION_ALIGNMENT_CHECK , EXCEPTION_SEVERE_MACHINE_CHECK
}
enum  _INTERRUPT_LIST {
  TIMER_INTERRUPT = 32 , KEYBOARD_INTERRUPT = 33 , ATA_INTERRUPT = 46 , LAPIC_INTERRUPT = 0xEF ,
  LAPIC_SIV_INTERRUPT = 0xFF
}
enum  _CPU_ACTION {
  CPU_ACTION_STOP = 0 , CPU_ACTION_PRINT_ID = 1 , CPU_ACTION_PERFORM_TLB_SHOOTDOWN = 2 , CPU_ACTION_WRITE_DEBUG_REGS = 3 ,
  CPU_ACTION_CLEAR_DEBUG_REGS = 4 , CPU_ACTION_DO_DEFERRED_ROUTINES = 5 , CPU_ACTION_FLUSH_CR3 = 6
}
enum  MADT_TYPES {
  MADT_LAPIC = 0 , MADT_IOAPIC = 1 , MADT_INTERUPT_SOURCE_OVERRIDE = 2 , MADT_NON_MASKABLE_INTERRUPT = 4 ,
  MADT_X2APIC = 9
}
enum  {
  CPUID_FEAT_ECX_SSE3 = 1 << 0 , CPUID_FEAT_ECX_PCLMUL = 1 << 1 , CPUID_FEAT_ECX_DTES64 = 1 << 2 , CPUID_FEAT_ECX_MONITOR = 1 << 3 ,
  CPUID_FEAT_ECX_DS_CPL = 1 << 4 , CPUID_FEAT_ECX_VMX = 1 << 5 , CPUID_FEAT_ECX_SMX = 1 << 6 , CPUID_FEAT_ECX_EST = 1 << 7 ,
  CPUID_FEAT_ECX_TM2 = 1 << 8 , CPUID_FEAT_ECX_SSSE3 = 1 << 9 , CPUID_FEAT_ECX_CID = 1 << 10 , CPUID_FEAT_ECX_SDBG = 1 << 11 ,
  CPUID_FEAT_ECX_FMA = 1 << 12 , CPUID_FEAT_ECX_CX16 = 1 << 13 , CPUID_FEAT_ECX_XTPR = 1 << 14 , CPUID_FEAT_ECX_PDCM = 1 << 15 ,
  CPUID_FEAT_ECX_PCID = 1 << 17 , CPUID_FEAT_ECX_DCA = 1 << 18 , CPUID_FEAT_ECX_SSE4_1 = 1 << 19 , CPUID_FEAT_ECX_SSE4_2 = 1 << 20 ,
  CPUID_FEAT_ECX_X2APIC = 1 << 21 , CPUID_FEAT_ECX_MOVBE = 1 << 22 , CPUID_FEAT_ECX_POPCNT = 1 << 23 , CPUID_FEAT_ECX_TSC = 1 << 24 ,
  CPUID_FEAT_ECX_AES = 1 << 25 , CPUID_FEAT_ECX_XSAVE = 1 << 26 , CPUID_FEAT_ECX_OSXSAVE = 1 << 27 , CPUID_FEAT_ECX_AVX = 1 << 28 ,
  CPUID_FEAT_ECX_F16C = 1 << 29 , CPUID_FEAT_ECX_RDRAND = 1 << 30 , CPUID_FEAT_ECX_HYPERVISOR = 1 << 31 , CPUID_FEAT_EDX_FPU = 1 << 0 ,
  CPUID_FEAT_EDX_VME = 1 << 1 , CPUID_FEAT_EDX_DE = 1 << 2 , CPUID_FEAT_EDX_PSE = 1 << 3 , CPUID_FEAT_EDX_TSC = 1 << 4 ,
  CPUID_FEAT_EDX_MSR = 1 << 5 , CPUID_FEAT_EDX_PAE = 1 << 6 , CPUID_FEAT_EDX_MCE = 1 << 7 , CPUID_FEAT_EDX_CX8 = 1 << 8 ,
  CPUID_FEAT_EDX_APIC = 1 << 9 , CPUID_FEAT_EDX_SEP = 1 << 11 , CPUID_FEAT_EDX_MTRR = 1 << 12 , CPUID_FEAT_EDX_PGE = 1 << 13 ,
  CPUID_FEAT_EDX_MCA = 1 << 14 , CPUID_FEAT_EDX_CMOV = 1 << 15 , CPUID_FEAT_EDX_PAT = 1 << 16 , CPUID_FEAT_EDX_PSE36 = 1 << 17 ,
  CPUID_FEAT_EDX_PSN = 1 << 18 , CPUID_FEAT_EDX_CLFLUSH = 1 << 19 , CPUID_FEAT_EDX_DS = 1 << 21 , CPUID_FEAT_EDX_ACPI = 1 << 22 ,
  CPUID_FEAT_EDX_MMX = 1 << 23 , CPUID_FEAT_EDX_FXSR = 1 << 24 , CPUID_FEAT_EDX_SSE = 1 << 25 , CPUID_FEAT_EDX_SSE2 = 1 << 26 ,
  CPUID_FEAT_EDX_SS = 1 << 27 , CPUID_FEAT_EDX_HTT = 1 << 28 , CPUID_FEAT_EDX_TM = 1 << 29 , CPUID_FEAT_EDX_IA64 = 1 << 30 ,
  CPUID_FEAT_EDX_PBE = 1 << 31
}

Functions

struct _RSDP_Descriptor __attribute__ ((packed)) RSDP_Descriptor
void APMain (void)
 ---------------— FUNCTIONS ---------------—
void MhInitializeSMP (uint8_t *apic_list, uint32_t cpu_count, uint32_t lapicAddress)
void MhSendActionToCpusAndWait (CPU_ACTION action, IPI_PARAMS parameter)
void set_idt_gate (int n, unsigned long int handler)
void install_idt (void)
void init_interrupts (void)
void lapic_init_cpu (void)
void lapic_enable (void)
uint32_t lapic_mmio_read (uint32_t off)
void lapic_mmio_write (uint32_t off, uint32_t val)
void lapic_eoi (void)
void lapic_init_siv (void)
void lapic_send_ipi (uint8_t apic_id, uint8_t vector, uint32_t flags)
int init_lapic_timer (uint32_t hz)
void pit_sleep_ms (uint32_t ms)
void lapic_timer_calibrate (void)
bool checkcpuid (void)
FORCEINLINE bool checkApic (void)
FORCEINLINE void getCpuName (char *name)
void MhHandleInterrupt (IN int vec_num, IN PTRAP_FRAME trap)
void MiLapicInterrupt (bool schedulerEnabled, PTRAP_FRAME trap)
void MiBreakpoint (PTRAP_FRAME trap)
NORETURN void MiNonMaskableInterrupt (PTRAP_FRAME trap)
void MiDivideByZero (PTRAP_FRAME trap)
void MiDebugTrap (PTRAP_FRAME trap)
NORETURN void MiDoubleFault (IN PTRAP_FRAME trap)
void MiInterprocessorInterrupt (void)
void MiPageFault (IN PTRAP_FRAME trap)
void MiInvalidTss (IN PTRAP_FRAME trap)
void MiOverflow (PTRAP_FRAME trap)
void MiBoundsCheck (PTRAP_FRAME trap)
void MiInvalidOpcode (PTRAP_FRAME trap)
void MiNoCoprocessor (PTRAP_FRAME trap)
void MiCoprocessorSegmentOverrun (PTRAP_FRAME trap)
void MiSegmentSelectorNotPresent (PTRAP_FRAME trap)
void MiStackSegmentOverrun (PTRAP_FRAME trap)
void MiGeneralProtectionFault (PTRAP_FRAME trap)
void MiFloatingPointError (PTRAP_FRAME trap)
void MiAlignmentCheck (PTRAP_FRAME trap)
void MiMachineCheck (PTRAP_FRAME trap)
void MhRequestSoftwareInterrupt (IN IRQL RequestIrql)
MTSTATUS MhInitializeACPI (void)
MTSTATUS MhParseLAPICs (uint8_t *buffer, size_t maxCPUs, uint32_t *cpuCount, uint32_t *lapicAddress)
void MhRebootComputer (void)

Variables

typedef __attribute__
char Signature [8]
uint8_t Checksum
char OemId [6]
uint8_t Revision
uint32_t RsdtAddress
uint32_t Length
uint64_t XsdtAddress
uint8_t ExtendedChecksum
uint8_t Reserved [3]
char OemTableId [8]
uint32_t OemRevision
uint32_t CreatorId
uint32_t CreatorRevision
struct _ACPI_SDT_HEADER h
uint64_t Entries []
uint8_t AddressSpace
uint8_t BitWidth
uint8_t BitOffset
uint8_t AccessSize
uint64_t Address
uint32_t FirmwareCtrl
uint32_t Dsdt
uint8_t PreferredPowerManagementProfile
uint16_t SCI_Interrupt
uint32_t SMI_CommandPort
uint8_t AcpiEnable
uint8_t AcpiDisable
uint8_t S4BIOS_REQ
uint8_t PSTATE_Control
uint32_t PM1aEventBlock
uint32_t PM1bEventBlock
uint32_t PM1aControlBlock
uint32_t PM1bControlBlock
uint32_t PM2ControlBlock
uint32_t PMTimerBlock
uint32_t GPE0Block
uint32_t GPE1Block
uint8_t PM1EventLength
uint8_t PM1ControlLength
uint8_t PM2ControlLength
uint8_t PMTimerLength
uint8_t GPE0Length
uint8_t GPE1Length
uint8_t GPE1Base
uint8_t CStateControl
uint16_t WorstC2Latency
uint16_t WorstC3Latency
uint16_t FlushSize
uint16_t FlushStride
uint8_t DutyOffset
uint8_t DutyWidth
uint8_t DayAlarm
uint8_t MonthAlarm
uint8_t Century
uint16_t BootArchitectureFlags
uint8_t Reserved2
uint32_t Flags
GenericAddressStructure ResetReg
uint8_t ResetValue
uint8_t Reserved3 [3]
uint64_t X_FirmwareControl
uint64_t X_Dsdt
GenericAddressStructure X_PM1aEventBlock
GenericAddressStructure X_PM1bEventBlock
GenericAddressStructure X_PM1aControlBlock
GenericAddressStructure X_PM1bControlBlock
GenericAddressStructure X_PM2ControlBlock
GenericAddressStructure X_PMTimerBlock
GenericAddressStructure X_GPE0Block
GenericAddressStructure X_GPE1Block
uint32_t lapicAddress
uint32_t flags
 GDTEntry64
 GDTPtr
 TSS
int smp_cpu_count
bool smpInitialized
bool allApsInitialized

Macro Definition Documentation

◆ AP_TRAMP_APMAIN_OFFSET

#define AP_TRAMP_APMAIN_OFFSET   0x1000ULL

Definition at line 405 of file mh.h.

◆ AP_TRAMP_CPUS_OFFSET

#define AP_TRAMP_CPUS_OFFSET   0x2500ULL

Definition at line 407 of file mh.h.

◆ AP_TRAMP_PHYS

#define AP_TRAMP_PHYS   0x7000ULL

Definition at line 403 of file mh.h.

◆ AP_TRAMP_PML4_OFFSET

#define AP_TRAMP_PML4_OFFSET   0x2000ULL

Definition at line 406 of file mh.h.

◆ AP_TRAMP_SIZE

#define AP_TRAMP_SIZE   0x1000UL

Definition at line 404 of file mh.h.

◆ CALC_VECTOR

#define CALC_VECTOR ( pri)
Value:
(IRQL_VECTOR_BASE + (pri << 4))
IRQL_VECTOR_BASE
#define IRQL_VECTOR_BASE
Definition mh.h:30

Definition at line 44 of file mh.h.

◆ CPUID_VENDOR_AMD

#define CPUID_VENDOR_AMD   "AuthenticAMD"

Definition at line 414 of file mh.h.

◆ CPUID_VENDOR_AMD_OLD

#define CPUID_VENDOR_AMD_OLD   "AMDisbetter!"

Definition at line 415 of file mh.h.

◆ CPUID_VENDOR_AO486

#define CPUID_VENDOR_AO486   "MiSTer AO486"

Definition at line 428 of file mh.h.

◆ CPUID_VENDOR_AO486_OLD

#define CPUID_VENDOR_AO486_OLD   "GenuineAO486"

Definition at line 429 of file mh.h.

◆ CPUID_VENDOR_BHYVE

#define CPUID_VENDOR_BHYVE   "bhyve bhyve "

Definition at line 443 of file mh.h.

◆ CPUID_VENDOR_CENTAUR

#define CPUID_VENDOR_CENTAUR   "CentaurHauls"

Definition at line 421 of file mh.h.

◆ CPUID_VENDOR_CYRIX

#define CPUID_VENDOR_CYRIX   "CyrixInstead"

Definition at line 420 of file mh.h.

◆ CPUID_VENDOR_ELBRUS

#define CPUID_VENDOR_ELBRUS   "E2K MACHINE "

Definition at line 432 of file mh.h.

◆ CPUID_VENDOR_HYGON

#define CPUID_VENDOR_HYGON   "HygonGenuine"

Definition at line 431 of file mh.h.

◆ CPUID_VENDOR_HYPERV

#define CPUID_VENDOR_HYPERV   "Microsoft Hv"

Definition at line 440 of file mh.h.

◆ CPUID_VENDOR_INTEL

#define CPUID_VENDOR_INTEL   "GenuineIntel"

Definition at line 416 of file mh.h.

◆ CPUID_VENDOR_KVM

#define CPUID_VENDOR_KVM   " KVMKVMKVM "

Definition at line 436 of file mh.h.

◆ CPUID_VENDOR_NEXGEN

#define CPUID_VENDOR_NEXGEN   "NexGenDriven"

Definition at line 422 of file mh.h.

◆ CPUID_VENDOR_NSC

#define CPUID_VENDOR_NSC   "Geode by NSC"

Definition at line 425 of file mh.h.

◆ CPUID_VENDOR_PARALLELS

#define CPUID_VENDOR_PARALLELS   " prl hyperv "

Definition at line 441 of file mh.h.

◆ CPUID_VENDOR_PARALLELS_ALT

#define CPUID_VENDOR_PARALLELS_ALT   " lrpepyh vr "

Definition at line 442 of file mh.h.

◆ CPUID_VENDOR_QEMU

#define CPUID_VENDOR_QEMU   "TCGTCGTCGTCG"

Definition at line 435 of file mh.h.

◆ CPUID_VENDOR_QNX

#define CPUID_VENDOR_QNX   " QNXQVMBSQG "

Definition at line 444 of file mh.h.

◆ CPUID_VENDOR_RISE

#define CPUID_VENDOR_RISE   "RiseRiseRise"

Definition at line 426 of file mh.h.

◆ CPUID_VENDOR_SIS

#define CPUID_VENDOR_SIS   "SiS SiS SiS "

Definition at line 424 of file mh.h.

◆ CPUID_VENDOR_TRANSMETA

#define CPUID_VENDOR_TRANSMETA   "GenuineTMx86"

Definition at line 418 of file mh.h.

◆ CPUID_VENDOR_TRANSMETA_OLD

#define CPUID_VENDOR_TRANSMETA_OLD   "TransmetaCPU"

Definition at line 419 of file mh.h.

◆ CPUID_VENDOR_UMC

#define CPUID_VENDOR_UMC   "UMC UMC UMC "

Definition at line 423 of file mh.h.

◆ CPUID_VENDOR_VIA

#define CPUID_VENDOR_VIA   "VIA VIA VIA "

Definition at line 417 of file mh.h.

◆ CPUID_VENDOR_VIRTUALBOX

#define CPUID_VENDOR_VIRTUALBOX   "VBoxVBoxVBox"

Definition at line 438 of file mh.h.

◆ CPUID_VENDOR_VMWARE

#define CPUID_VENDOR_VMWARE   "VMwareVMware"

Definition at line 437 of file mh.h.

◆ CPUID_VENDOR_VORTEX

#define CPUID_VENDOR_VORTEX   "Vortex86 SoC"

Definition at line 427 of file mh.h.

◆ CPUID_VENDOR_XEN

#define CPUID_VENDOR_XEN   "XenVMMXenVMM"

Definition at line 439 of file mh.h.

◆ CPUID_VENDOR_ZHAOXIN

#define CPUID_VENDOR_ZHAOXIN   " Shanghai "

Definition at line 430 of file mh.h.

◆ IDT_ENTRIES

#define IDT_ENTRIES   256

Definition at line 26 of file mh.h.

◆ IRQL_VECTOR_BASE

#define IRQL_VECTOR_BASE   0x40

Definition at line 30 of file mh.h.

◆ IST_ALIGNMENT

#define IST_ALIGNMENT   16

Definition at line 412 of file mh.h.

◆ IST_SIZE

#define IST_SIZE   (16*1024)

Definition at line 411 of file mh.h.

◆ LAPIC_ID

#define LAPIC_ID   0x020

Definition at line 409 of file mh.h.

◆ LAPIC_TIMER_VECTOR

#define LAPIC_TIMER_VECTOR   0xEF

Definition at line 50 of file mh.h.

◆ MAX_CPUS

#define MAX_CPUS   32

Definition at line 408 of file mh.h.

◆ SMP_MAGIC

#define SMP_MAGIC   0x4D4154414E454C00

Definition at line 410 of file mh.h.

◆ TPR_APC

#define TPR_APC   3

Definition at line 38 of file mh.h.

◆ TPR_DPC

#define TPR_DPC   8

Definition at line 39 of file mh.h.

◆ TPR_IPI

#define TPR_IPI   11

Definition at line 41 of file mh.h.

◆ TPR_PASSIVE

#define TPR_PASSIVE   0

Definition at line 37 of file mh.h.

◆ TPR_PROFILE

#define TPR_PROFILE   10

Definition at line 40 of file mh.h.

◆ VECTOR_APC

#define VECTOR_APC   CALC_VECTOR(TPR_APC)

Definition at line 48 of file mh.h.

◆ VECTOR_DPC

#define VECTOR_DPC   CALC_VECTOR(TPR_DPC)

Definition at line 47 of file mh.h.

◆ VECTOR_IPI

#define VECTOR_IPI   CALC_VECTOR(TPR_IPI)

Definition at line 49 of file mh.h.

Typedef Documentation

◆ CPU_ACTION

typedef enum _CPU_ACTION CPU_ACTION

◆ CPU_EXCEPTIONS

typedef enum _CPU_EXCEPTIONS CPU_EXCEPTIONS

◆ DEBUG_REGISTERS

typedef struct _DEBUG_REGISTERS DEBUG_REGISTERS

◆ DebugCallback

typedef void(* DebugCallback) (void *)

Definition at line 385 of file mh.h.

◆ IDT_ENTRY64

typedef struct _IDT_ENTRY_64 IDT_ENTRY64

◆ IDT_PTR

typedef struct _IDT_PTR IDT_PTR

◆ INTERRUPT_LIST

typedef enum _INTERRUPT_LIST INTERRUPT_LIST

Interrupt Definitions

◆ IPI_PARAMS

typedef struct _IPI_PARAMS IPI_PARAMS

◆ PAGE_PARAMETERS

typedef struct _PAGE_PARAMETERS PAGE_PARAMETERS

◆ SMP_BOOTINFO

typedef struct _SMP_BOOTINFO SMP_BOOTINFO

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
CPUID_FEAT_ECX_SSE3 
CPUID_FEAT_ECX_PCLMUL 
CPUID_FEAT_ECX_DTES64 
CPUID_FEAT_ECX_MONITOR 
CPUID_FEAT_ECX_DS_CPL 
CPUID_FEAT_ECX_VMX 
CPUID_FEAT_ECX_SMX 
CPUID_FEAT_ECX_EST 
CPUID_FEAT_ECX_TM2 
CPUID_FEAT_ECX_SSSE3 
CPUID_FEAT_ECX_CID 
CPUID_FEAT_ECX_SDBG 
CPUID_FEAT_ECX_FMA 
CPUID_FEAT_ECX_CX16 
CPUID_FEAT_ECX_XTPR 
CPUID_FEAT_ECX_PDCM 
CPUID_FEAT_ECX_PCID 
CPUID_FEAT_ECX_DCA 
CPUID_FEAT_ECX_SSE4_1 
CPUID_FEAT_ECX_SSE4_2 
CPUID_FEAT_ECX_X2APIC 
CPUID_FEAT_ECX_MOVBE 
CPUID_FEAT_ECX_POPCNT 
CPUID_FEAT_ECX_TSC 
CPUID_FEAT_ECX_AES 
CPUID_FEAT_ECX_XSAVE 
CPUID_FEAT_ECX_OSXSAVE 
CPUID_FEAT_ECX_AVX 
CPUID_FEAT_ECX_F16C 
CPUID_FEAT_ECX_RDRAND 
CPUID_FEAT_ECX_HYPERVISOR 
CPUID_FEAT_EDX_FPU 
CPUID_FEAT_EDX_VME 
CPUID_FEAT_EDX_DE 
CPUID_FEAT_EDX_PSE 
CPUID_FEAT_EDX_TSC 
CPUID_FEAT_EDX_MSR 
CPUID_FEAT_EDX_PAE 
CPUID_FEAT_EDX_MCE 
CPUID_FEAT_EDX_CX8 
CPUID_FEAT_EDX_APIC 
CPUID_FEAT_EDX_SEP 
CPUID_FEAT_EDX_MTRR 
CPUID_FEAT_EDX_PGE 
CPUID_FEAT_EDX_MCA 
CPUID_FEAT_EDX_CMOV 
CPUID_FEAT_EDX_PAT 
CPUID_FEAT_EDX_PSE36 
CPUID_FEAT_EDX_PSN 
CPUID_FEAT_EDX_CLFLUSH 
CPUID_FEAT_EDX_DS 
CPUID_FEAT_EDX_ACPI 
CPUID_FEAT_EDX_MMX 
CPUID_FEAT_EDX_FXSR 
CPUID_FEAT_EDX_SSE 
CPUID_FEAT_EDX_SSE2 
CPUID_FEAT_EDX_SS 
CPUID_FEAT_EDX_HTT 
CPUID_FEAT_EDX_TM 
CPUID_FEAT_EDX_IA64 
CPUID_FEAT_EDX_PBE 

Definition at line 109 of file mh.h.

◆ _CPU_ACTION

enum _CPU_ACTION
Enumerator
CPU_ACTION_STOP 
CPU_ACTION_PRINT_ID 
CPU_ACTION_PERFORM_TLB_SHOOTDOWN 
CPU_ACTION_WRITE_DEBUG_REGS 
CPU_ACTION_CLEAR_DEBUG_REGS 
CPU_ACTION_DO_DEFERRED_ROUTINES 
CPU_ACTION_FLUSH_CR3 

Definition at line 91 of file mh.h.

◆ _CPU_EXCEPTIONS

enum _CPU_EXCEPTIONS
Enumerator
EXCEPTION_DIVIDE_BY_ZERO 
EXCEPTION_SINGLE_STEP 
EXCEPTION_NON_MASKABLE_INTERRUPT 
EXCEPTION_BREAKPOINT 
EXCEPTION_OVERFLOW 
EXCEPTION_BOUNDS_CHECK 
EXCEPTION_INVALID_OPCODE 
EXCEPTION_NO_COPROCESSOR 
EXCEPTION_DOUBLE_FAULT 
EXCEPTION_COPROCESSOR_SEGMENT_OVERRUN 
EXCEPTION_INVALID_TSS 
EXCEPTION_SEGMENT_SELECTOR_NOTPRESENT 
EXCEPTION_STACK_SEGMENT_OVERRUN 
EXCEPTION_GENERAL_PROTECTION_FAULT 
EXCEPTION_PAGE_FAULT 
EXCEPTION_RESERVED 
EXCEPTION_FLOATING_POINT_ERROR 
EXCEPTION_ALIGNMENT_CHECK 
EXCEPTION_SEVERE_MACHINE_CHECK 

Definition at line 60 of file mh.h.

◆ _INTERRUPT_LIST

enum _INTERRUPT_LIST

Interrupt Definitions

Enumerator
TIMER_INTERRUPT 
KEYBOARD_INTERRUPT 
ATA_INTERRUPT 
LAPIC_INTERRUPT 
LAPIC_SIV_INTERRUPT 

Definition at line 83 of file mh.h.

◆ MADT_TYPES

enum MADT_TYPES
Enumerator
MADT_LAPIC 
MADT_IOAPIC 
MADT_INTERUPT_SOURCE_OVERRIDE 
MADT_NON_MASKABLE_INTERRUPT 
MADT_X2APIC 

Definition at line 101 of file mh.h.

Function Documentation

◆ __attribute__()

struct _RSDP_Descriptor __attribute__ ( (packed) )

Definition at line 52 of file mh.h.

◆ APMain()

void APMain ( void )

---------------— FUNCTIONS ---------------—

Definition at line 35 of file ap_main.c.

◆ checkApic()

FORCEINLINE bool checkApic ( void )

Definition at line 488 of file mh.h.

◆ checkcpuid()

bool checkcpuid ( void )
extern

◆ getCpuName()

FORCEINLINE void getCpuName ( char * name)

Definition at line 495 of file mh.h.

◆ init_interrupts()

void init_interrupts ( void )

Definition at line 168 of file isr.c.

◆ init_lapic_timer()

int init_lapic_timer ( uint32_t hz)

Definition at line 179 of file apic.c.

◆ install_idt()

void install_idt ( void )

Definition at line 24 of file idt.c.

◆ lapic_enable()

void lapic_enable ( void )

Definition at line 98 of file apic.c.

◆ lapic_eoi()

void lapic_eoi ( void )

Definition at line 136 of file apic.c.

◆ lapic_init_cpu()

void lapic_init_cpu ( void )

Definition at line 113 of file apic.c.

◆ lapic_init_siv()

void lapic_init_siv ( void )

Definition at line 60 of file apic.c.

◆ lapic_mmio_read()

uint32_t lapic_mmio_read ( uint32_t off)

Definition at line 36 of file apic.c.

◆ lapic_mmio_write()

void lapic_mmio_write ( uint32_t off,
uint32_t val )

Definition at line 45 of file apic.c.

◆ lapic_send_ipi()

void lapic_send_ipi ( uint8_t apic_id,
uint8_t vector,
uint32_t flags )

Definition at line 129 of file apic.c.

◆ lapic_timer_calibrate()

void lapic_timer_calibrate ( void )

Definition at line 171 of file apic.c.

◆ MhHandleInterrupt()

void MhHandleInterrupt ( IN int vec_num,
IN PTRAP_FRAME trap )

Definition at line 27 of file isr.c.

◆ MhInitializeACPI()

MTSTATUS MhInitializeACPI ( void )

Definition at line 164 of file acpi.c.

◆ MhInitializeSMP()

void MhInitializeSMP ( uint8_t * apic_list,
uint32_t cpu_count,
uint32_t lapicAddress )

Definition at line 132 of file smp.c.

◆ MhParseLAPICs()

MTSTATUS MhParseLAPICs ( uint8_t * buffer,
size_t maxCPUs,
uint32_t * cpuCount,
uint32_t * lapicAddress )

Definition at line 130 of file acpi.c.

◆ MhRebootComputer()

void MhRebootComputer ( void )

Definition at line 83 of file acpi.c.

◆ MhRequestSoftwareInterrupt()

void MhRequestSoftwareInterrupt ( IN IRQL RequestIrql)

Definition at line 199 of file apic.c.

◆ MhSendActionToCpusAndWait()

void MhSendActionToCpusAndWait ( CPU_ACTION action,
IPI_PARAMS parameter )

Definition at line 212 of file smp.c.

◆ MiAlignmentCheck()

void MiAlignmentCheck ( PTRAP_FRAME trap)

Definition at line 468 of file handlers.c.

◆ MiBoundsCheck()

void MiBoundsCheck ( PTRAP_FRAME trap)

Definition at line 420 of file handlers.c.

◆ MiBreakpoint()

void MiBreakpoint ( PTRAP_FRAME trap)

Definition at line 392 of file handlers.c.

◆ MiCoprocessorSegmentOverrun()

void MiCoprocessorSegmentOverrun ( PTRAP_FRAME trap)

Definition at line 434 of file handlers.c.

◆ MiDebugTrap()

void MiDebugTrap ( PTRAP_FRAME trap)

Definition at line 298 of file handlers.c.

◆ MiDivideByZero()

void MiDivideByZero ( PTRAP_FRAME trap)

Definition at line 258 of file handlers.c.

◆ MiDoubleFault()

NORETURN void MiDoubleFault ( IN PTRAP_FRAME trap)

Definition at line 226 of file handlers.c.

◆ MiFloatingPointError()

void MiFloatingPointError ( PTRAP_FRAME trap)

Definition at line 462 of file handlers.c.

◆ MiGeneralProtectionFault()

void MiGeneralProtectionFault ( PTRAP_FRAME trap)

Definition at line 457 of file handlers.c.

◆ MiInterprocessorInterrupt()

void MiInterprocessorInterrupt ( void )

Definition at line 70 of file handlers.c.

◆ MiInvalidOpcode()

void MiInvalidOpcode ( PTRAP_FRAME trap)

Definition at line 425 of file handlers.c.

◆ MiInvalidTss()

void MiInvalidTss ( IN PTRAP_FRAME trap)

Definition at line 439 of file handlers.c.

◆ MiLapicInterrupt()

void MiLapicInterrupt ( bool schedulerEnabled,
PTRAP_FRAME trap )

Definition at line 65 of file handlers.c.

◆ MiMachineCheck()

void MiMachineCheck ( PTRAP_FRAME trap)

Definition at line 478 of file handlers.c.

◆ MiNoCoprocessor()

void MiNoCoprocessor ( PTRAP_FRAME trap)

Definition at line 429 of file handlers.c.

◆ MiNonMaskableInterrupt()

NORETURN void MiNonMaskableInterrupt ( PTRAP_FRAME trap)

Definition at line 362 of file handlers.c.

◆ MiOverflow()

void MiOverflow ( PTRAP_FRAME trap)

Definition at line 416 of file handlers.c.

◆ MiPageFault()

void MiPageFault ( IN PTRAP_FRAME trap)

Definition at line 155 of file handlers.c.

◆ MiSegmentSelectorNotPresent()

void MiSegmentSelectorNotPresent ( PTRAP_FRAME trap)

Definition at line 445 of file handlers.c.

◆ MiStackSegmentOverrun()

void MiStackSegmentOverrun ( PTRAP_FRAME trap)

Definition at line 451 of file handlers.c.

◆ pit_sleep_ms()

void pit_sleep_ms ( uint32_t ms)

Definition at line 19 of file pit.c.

◆ set_idt_gate()

void set_idt_gate ( int n,
unsigned long int handler )

Definition at line 13 of file idt.c.

Variable Documentation

◆ __attribute__

struct __attribute__

Definition at line 54 of file fat32.h.

◆ AccessSize

uint8_t AccessSize

Definition at line 3 of file mh.h.

◆ AcpiDisable

uint8_t AcpiDisable

Definition at line 11 of file mh.h.

◆ AcpiEnable

uint8_t AcpiEnable

Definition at line 10 of file mh.h.

◆ Address

uint64_t Address

Definition at line 4 of file mh.h.

◆ AddressSpace

uint8_t AddressSpace

Definition at line 0 of file mh.h.

◆ allApsInitialized

bool allApsInitialized
extern

Definition at line 20 of file kernel.c.

◆ BitOffset

uint8_t BitOffset

Definition at line 2 of file mh.h.

◆ BitWidth

uint8_t BitWidth

Definition at line 1 of file mh.h.

◆ BootArchitectureFlags

uint16_t BootArchitectureFlags

Definition at line 41 of file mh.h.

◆ Century

uint8_t Century

Definition at line 38 of file mh.h.

◆ Checksum

uint8_t Checksum

Definition at line 1 of file mh.h.

◆ CreatorId

uint32_t CreatorId

Definition at line 7 of file mh.h.

◆ CreatorRevision

uint32_t CreatorRevision

Definition at line 8 of file mh.h.

◆ CStateControl

uint8_t CStateControl

Definition at line 29 of file mh.h.

◆ DayAlarm

uint8_t DayAlarm

Definition at line 36 of file mh.h.

◆ Dsdt

uint32_t Dsdt

Definition at line 2 of file mh.h.

◆ DutyOffset

uint8_t DutyOffset

Definition at line 34 of file mh.h.

◆ DutyWidth

uint8_t DutyWidth

Definition at line 35 of file mh.h.

◆ Entries

uint64_t Entries[]

Definition at line 1 of file mh.h.

◆ ExtendedChecksum

uint8_t ExtendedChecksum

Definition at line 8 of file mh.h.

◆ FirmwareCtrl

uint32_t FirmwareCtrl

Definition at line 1 of file mh.h.

◆ Flags

uint32_t Flags

Definition at line 44 of file mh.h.

◆ flags

uint32_t flags

Definition at line 2 of file mh.h.

◆ FlushSize

uint16_t FlushSize

Definition at line 32 of file mh.h.

◆ FlushStride

uint16_t FlushStride

Definition at line 33 of file mh.h.

◆ GDTEntry64

GDTEntry64

Definition at line 366 of file mh.h.

◆ GDTPtr

GDTPtr

Definition at line 371 of file mh.h.

◆ GPE0Block

uint32_t GPE0Block

Definition at line 20 of file mh.h.

◆ GPE0Length

uint8_t GPE0Length

Definition at line 26 of file mh.h.

◆ GPE1Base

uint8_t GPE1Base

Definition at line 28 of file mh.h.

◆ GPE1Block

uint32_t GPE1Block

Definition at line 21 of file mh.h.

◆ GPE1Length

uint8_t GPE1Length

Definition at line 27 of file mh.h.

◆ h

struct _ACPI_SDT_HEADER h

Definition at line 0 of file mh.h.

◆ lapicAddress

uint32_t lapicAddress

Definition at line 1 of file mh.h.

◆ Length

uint32_t Length

Definition at line 6 of file mh.h.

◆ MonthAlarm

uint8_t MonthAlarm

Definition at line 37 of file mh.h.

◆ OemId

char OemId

Definition at line 2 of file mh.h.

◆ OemRevision

uint32_t OemRevision

Definition at line 6 of file mh.h.

◆ OemTableId

char OemTableId[8]

Definition at line 5 of file mh.h.

◆ PM1aControlBlock

uint32_t PM1aControlBlock

Definition at line 16 of file mh.h.

◆ PM1aEventBlock

uint32_t PM1aEventBlock

Definition at line 14 of file mh.h.

◆ PM1bControlBlock

uint32_t PM1bControlBlock

Definition at line 17 of file mh.h.

◆ PM1bEventBlock

uint32_t PM1bEventBlock

Definition at line 15 of file mh.h.

◆ PM1ControlLength

uint8_t PM1ControlLength

Definition at line 23 of file mh.h.

◆ PM1EventLength

uint8_t PM1EventLength

Definition at line 22 of file mh.h.

◆ PM2ControlBlock

uint32_t PM2ControlBlock

Definition at line 18 of file mh.h.

◆ PM2ControlLength

uint8_t PM2ControlLength

Definition at line 24 of file mh.h.

◆ PMTimerBlock

uint32_t PMTimerBlock

Definition at line 19 of file mh.h.

◆ PMTimerLength

uint8_t PMTimerLength

Definition at line 25 of file mh.h.

◆ PreferredPowerManagementProfile

uint8_t PreferredPowerManagementProfile

Definition at line 7 of file mh.h.

◆ PSTATE_Control

uint8_t PSTATE_Control

Definition at line 13 of file mh.h.

◆ Reserved

uint8_t Reserved

Definition at line 9 of file mh.h.

◆ Reserved2

uint8_t Reserved2

Definition at line 43 of file mh.h.

◆ Reserved3

uint8_t Reserved3[3]

Definition at line 50 of file mh.h.

◆ ResetReg

GenericAddressStructure ResetReg

Definition at line 47 of file mh.h.

◆ ResetValue

uint8_t ResetValue

Definition at line 49 of file mh.h.

◆ Revision

uint8_t Revision

Definition at line 3 of file mh.h.

◆ RsdtAddress

uint32_t RsdtAddress

Definition at line 4 of file mh.h.

◆ S4BIOS_REQ

uint8_t S4BIOS_REQ

Definition at line 12 of file mh.h.

◆ SCI_Interrupt

uint16_t SCI_Interrupt

Definition at line 8 of file mh.h.

◆ Signature

char Signature

Definition at line 0 of file mh.h.

◆ SMI_CommandPort

uint32_t SMI_CommandPort

Definition at line 9 of file mh.h.

◆ smp_cpu_count

int smp_cpu_count
extern

Definition at line 17 of file smp.c.

◆ smpInitialized

bool smpInitialized
extern

Definition at line 146 of file kernel.c.

◆ TSS

TSS

Definition at line 383 of file mh.h.

◆ WorstC2Latency

uint16_t WorstC2Latency

Definition at line 30 of file mh.h.

◆ WorstC3Latency

uint16_t WorstC3Latency

Definition at line 31 of file mh.h.

◆ X_Dsdt

uint64_t X_Dsdt

Definition at line 54 of file mh.h.

◆ X_FirmwareControl

uint64_t X_FirmwareControl

Definition at line 53 of file mh.h.

◆ X_GPE0Block

GenericAddressStructure X_GPE0Block

Definition at line 62 of file mh.h.

◆ X_GPE1Block

GenericAddressStructure X_GPE1Block

Definition at line 63 of file mh.h.

◆ X_PM1aControlBlock

GenericAddressStructure X_PM1aControlBlock

Definition at line 58 of file mh.h.

◆ X_PM1aEventBlock

GenericAddressStructure X_PM1aEventBlock

Definition at line 56 of file mh.h.

◆ X_PM1bControlBlock

GenericAddressStructure X_PM1bControlBlock

Definition at line 59 of file mh.h.

◆ X_PM1bEventBlock

GenericAddressStructure X_PM1bEventBlock

Definition at line 57 of file mh.h.

◆ X_PM2ControlBlock

GenericAddressStructure X_PM2ControlBlock

Definition at line 60 of file mh.h.

◆ X_PMTimerBlock

GenericAddressStructure X_PMTimerBlock

Definition at line 61 of file mh.h.

◆ XsdtAddress

uint64_t XsdtAddress

Definition at line 7 of file mh.h.